As computer devices and systems continue to advance and become more complex, effective and efficient techniques for transferring data between various components in data communication systems have become more and more critical in system design and implementation. Generally, in high speed data communication systems, it is desirable to transfer data in parallel form (e.g., via a parallel bus or parallel link) at the highest possible speed to allow a good trade off between the parallel width of the bus and the speed capabilities of the respective components. Current technologies allow data transfer between components at such high speeds that variations in distance between individual bits of a parallel bus may cause significant electrical skew of the bus. In general, current data communication systems or applications employ various techniques to accommodate delay variations in the round trip delay of the transmit path. However, traditional or conventional techniques only account for variations of one of the signals of a parallel bus (e.g., the transmit clock signal, etc.) but not for delay variations with respect to individual bits of a parallel bus. Accordingly, current methods or techniques to accommodate delay variations are not effective in high speed data communication systems where variations in distance between individual bits of a parallel bus may cause significant electrical skew of the bus.